The present invention relates to digital data encoding circuitry. More particularly, the present invention relates to a synchronously operated digital state machine circuit for encoding a succession of data bits from a Non-Return-to-Zero (NRZ) format to a Coded Marked Inversion (CMI) format.
In applications relating to the transmission of digital data from a transmitter to a receiver via an optical fiber link, for example, the format of the transmitted optical signal is critical in maintaining the integrity of the data. The format must permit the decision circuity in the receiver to extract precise timing information from the incoming optical signal. As is well known, timing serves three essential purposes, namely, allowing the receiver to sample the signal at the time the signal-to-noise ratio is a maximum, maintaining the proper pulse spacing, and indicating the start and end of each timing interval.
In addition, since errors resulting from noise and distortion can occur in the signal detection process, it may be desirable for the optical signal to have an inherent error-detecting capability. These features can be incorporated into the data stream by encoding the signal according to, for example, the Coded Marked Inversion or CMI format, which is a well-known technique.
The CMI format is a two-level line code in which digital data is converted into a pair of data bits. An example of a stream of digital data converted from the NRZ format to the CMI format is shown in FIG. 1. Specifically, an NRZ data bit of "0" is converted into a pair of data bits "0,1" and an NRZ data bit of "1" is converted alternately into a pair of data bits "0,0" and "1,1". The pair of data bits "1,0" is, by definition, an illegal combination. The converted pair of data bits (i.e., "0,1" "0,0", or "1,1") is transmitted within the same clock period, that is, time frame or data period in which the NRZ digital data is applied to the encoding unit.
In general, circuits or transmitters which encode a stream of digital data from the NRZ format to the CMI format are known. For example, U.S. Pat. No. 4,189,621 to Scott describes a device for encoding NRZ data into the CMI format. Scott discloses a circuit providing first, second, and third signal channels and an output gating circuit. The first signal channel includes an input connected to receive clock-related pulses and a delay circuit for delaying the clock-related pulses by a predetermined amount of time. The second signal channel includes an input connected to receive the clock-related pulses, an input connected to receive NRZ signals to be encoded in the CMI format, and other logic for deriving from the input NRZ signals a sequence of signals related to Return-to Zero (RZ) signals divided by two. The third signal channel is connected to receive NRZ signals and to derive signals related to these NRZ signals. The output gating circuit is connected to receive the signals from the three signal channels for logically combining the output signals from the second and third signal channels in order to derive a sequence of control signals to be supplied to a clock switching circuit connected to the first signal channel. The delay caused by the delay circuit to the clock-related pulses from the first signal channel relative to the delay of the control signals from the second and third signal channels is approximately plus/minus a quarter clock period. This delay circuit presents a major disadvantage in the Scott circuit.
Typically, delay circuits, particularly those used for delaying clock signals as in Scott, introduce many uncertainties in digital circuits, and such circuits are considered inferior to a completely synchronous circuit. Moreover, components of a delay circuit require very precise tolerances and, in general, are more expensive than in synchronous circuits. Accordingly, synchronous designs are preferred.
The device of Scott is further disadvantageous in that no means of minimizing the effects of noise is provided.
U.S. Pat. No. 5,107,263 to Kim et al. is another patent relating to an encoding circuit for converting NRZ data to CMI format. Kim et al., like Scott, also utilizes a delay circuit for encoding the incoming stream of NRZ data to CMI format. Kim et al. therefore suffers from some of the same disadvantages as does the circuitry disclosed by Scott.
Lastly, U.S. Pat. No. 5,113,187 to the same inventor, Gorshe, and commonly assigned as the present application, relates to a CMI encoder circuit having a completely synchronous and digital implementation for encoding a stream of NRZ digital data in CMI format. This encoder was constructed in the form of a state machine having both legal and illegal states. While the state machine described in U.S. Pat. No. 5,113,187 avoids the use of delay circuits and components as used in both Scott and Kim et al., it nevertheless has disadvantages. In particular, the encoder described in this earlier patent includes a state machine having both a set of legal states and illegal states. Once the state machine transitions into one of the illegal states, it remains there until the illegal state condition is detected. Thus, the encoder required additional hardware components for detecting when the state machine enters one of the illegal states and for returning the state machine back to a legal state.